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? 2014 microchip technology inc. ds00001759b-page 1 highlights ? integrated usb power delivery (pd) phy ? support for power delivery message protocol ? integrated voltage and current adc inputs ? configuration profile selection ? on-chip microcontroller ? spi interface ? commercial and industrial grade temperature support ? available in 32-sqfn package target applications ? ac adapters & chargers - type-a - type-b -micro-a -micro-b - captive cable key benefits ? integrated usb power delivery (pd) phy - integrated receive termination - requires minimal external components ? support for power delivery message protocol - message generation/consumption - retry generation - error handling - state behavior ? cable detect logic - cable attachment type ? cfg_sel pins allow selection of multiple profiles - provider - consumer/provider ? integrated voltage (vmon) and current (imon) adc inputs ? dead battery support ? on-chip microcontroller - manages i/os and other signals - implements power delivery policy engine and device policy manager ? configuration programming via otp, or vendor defined messaging ? supports low power modes ? serial peripheral interface (spi) bus ? internal 3.3 v and 1. 8 v voltage regulators ? integrated oscillator reduces bom costs ? package - 32-pin sqfn (5 x 5 mm) ? environmental - commercial temperature range (0c to +70c) - industrial temperature range (-40c to +85c UPD1001 usb power delivery controller
UPD1001 ds00001759b-page 2 ? 2014 microchip technology inc. to our valued customers it is our intention to provide our valued customers with the bes t documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regarding this publication, please contact the marketing co mmunications department via e-mail at docerrors@microchip.com . we welcome your feedback. most current documentation to obtain the most up-to-date version of this document ation, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data s heet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the versi on number, (e.g., ds30000000a is version a of document ds30000000). errata an errata sheet, describing minor operati onal differences from the data sheet and recommended workarounds, may exist for cur- rent devices. as device/doc umentation issues become known to us, we will publish an errata s heet. the errata will specify the revision of silicon and revision of document to which it applies. to determine if an errata sheet exis ts for a particular device, please check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) when contacting a sales office, please spec ify which device, revision of silicon and data sheet (include -literature number) yo u are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products.
? 2014 microchip technology inc. ds00001759b-page 3 UPD1001 table of contents 1.0 introduction .............................................................................................................. ....................................................................... 4 2.0 pin descriptions and configuration ........................................................................................ ......................................................... 6 3.0 functional descriptions ................................................................................................... .............................................................. 19 4.0 operational charac teristics ............................................................................................... ............................................................ 33 5.0 package outline ........................................................................................................... ................................................................. 37 6.0 revision history .......................................................................................................... .................................................................. 38 the microchip web site ........................................................................................................ .............................................................. 39 customer change notification service .......................................................................................... ..................................................... 39 customer support .............................................................................................................. ................................................................. 39 product identification system ................................................................................................. ............................................................ 40
UPD1001 ds00001759b-page 4 ? 2014 microchip technology inc. 1.0 introduction 1.1 general description the UPD1001 is a usb power delivery (pd) controller designed to adhere to the usb power delivery specification . usb power delivery allows a host (or de vice) to provide or consume up to 5 amps and/or up to 20 volts of power from a usb pd capable partner device on the other end of the usb cable. usb pd capable standard and custom cables/ connectors are supported, which in most cases ar e backward compatible with standard usb connections. the UPD1001 provides a complete usb power delivery solution for all charger and adapter solutions. the functionality of the UPD1001 is selected via two configuration selection pins, cfg_sel0 and cfg_sel1 , which can be used to select unique pd and system configurations. designing the up d1001 into a system can be as simple as selecting a configuration, with no external eeprom required. advanced programmability options exist with an external eeprom installed. the integrated usb power delivery mac and phy support provider and consumer operation via the pd communication protocol, as specified in revi sion 1.0 (version 1.2) of the usb power delivery specification . monitoring of vbus and battery charging is accomplished via the integrated voltag e and current adc inputs. the phy supports cable id detec- tion/identification and loopback modes. the phy includes a 24mhz fsk modulator/demodulator and provides inte- grated terminations. the usb pd mac supports both usb pd insertion detection (cold socket) and dead battery cases. the on-chip microcontroller manages the ios and implements the power delivery local policy engine and device man- ager. the spi rom controller is used by the microcontroller for optional external code execution from rom. a one time programmable (otp) rom is integrated in the UPD1001. integrated 3.3 v and 1. 8 v regulators allow device operation from a single power supply. the UPD1001 is available in co mmercial (0c to +70c) and industrial (-40c to +85c) temperature ranges. an internal block diagram of the UPD1001 is shown in figure 1-1 . the UPD1001 is offered in a 32-pin sqfn package. the pack age provides multiple pin configurations, based upon the cfg_sel0 and cfg_sel1 configuration select signals. ta b l e 1 - 1 summarizes the available pin combinations and their target applications. refer to section 2.0, "pin descriptions and configuration," on page 6 for detailed information on specific pin configurations. table 1-1: UPD1001 package/pin configuration summary package pin config. name pd role usb receptacle notes 32-sqfn 32-a provider standard-a (std-a) see section 2.1 for pin assignments 32-b consumer/provider standard-b (std-b) see section 2.1 for pin assignments
? 2014 microchip technology inc. ds00001759b-page 5 UPD1001 figure 1-1: internal block diagram power delivery afe power delivery mac pd_data pd_id configuration select cfg_sel0 cfg_sel1 voltage monitor vmon clocks micro- controller spi rom controller current monitor imon spi rom i/o controller ? i/o ? specific functions are determined by package and cfg_sel0 / cfg_sel1 profile selection. reset_n reset controller voltage switch ? vbus ? vtr UPD1001
UPD1001 ds00001759b-page 6 ? 2014 microchip technology inc. 2.0 pin descriptions and configuration the pinouts for the package, along with system-level applic ation diagrams, are detailed in the following section: ? 32-pin sqfn (32-sqfn) note: for a summary of the available pin combinations and their corresponding target applications, refer to table 1-1 . pin descriptions are detailed in section 2.2, "pin descriptions," on page 10 . for details on the cfg_sel0 and cfg_- sel1 configuration select signals, refer to section 3.3, "configuration sele ction (cfg_sel0/cfg_sel1)," on page 20 . 2.1 32-pin sqfn (32-sqfn) 2.1.1 32-sqfn pin diagram note: when an ? _n ? is used at the end of the signal name, it indica tes that the signal is active low. for example, reset_n indicates that the reset signal is active low. figure 2-1: 32-sqfn pin assignments (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 cfg_sel1 cfg_sel0 ifault vdd33_cap vbus vsw_cap vtr vdd18a_cap pd_data pd_id pd_vdd18 vddio imon vmon vsel3_n vsel2_n vbus_discharge fault_n vsel1_n pd_detect/vsafedb_en* insertion_detect/bulk_cap* spi_rom_di spi_rom_do spi_rom_clk spi_rom_ce_n test vdd18_cap reset_n chg_emu_en/nc* vsel0_n vddio pd_en_n (connect exposed pad to ground with a via field) vss UPD1001 32-sqfn (top view) note: exposed pad (vss ) on bottom of package must be conn ected to ground with a via field. * the functionality of this pin is dependent on the cfg_sel0 / cfg_sel1 profile selection.
? 2014 microchip technology inc. ds00001759b-page 7 UPD1001 note: the buffer type for each signal is indicated in the buffer type column of table 2-2, "pin descriptions" . a description of the buffer types is provided in section 2.3, "buffer types" . 2.1.2 32-sqfn pin assignments the UPD1001 32-sqfn provides two distinct pin c onfigurations (32-a and 32-b) based upon the cfg_sel0 and cfg_sel1 configuration select pins. the 32-a and 32-b pin configurations are designed for use with usb standard- a and standard-b receptacles, respectively, and are detailed in ta b l e 2 - 1 . for pin descriptions, refer to section 2.2, "pin descriptions" . for example connection diagrams, refer to section 2.4, "power conn ection diagram," on page 18 . for information on the configuration select pins, refer to section 3.3, "configuration selection (cfg_sel0/cfg_sel1)" . note: the 32-a and 32-b pin configuration assignments differ only on pins 14, 15, and 16. table 2-1: 32-sqfn package pin assignments pin number configuration 32-a name configuration 32-b name 1 cfg_sel0 2 cfg_sel1 3 ifault 4 vdd33_cap 5 vbus 6 vsw_cap 7 vtr 8 vdd18a_cap 9 spi_rom_ce_n 10 spi_rom_clk 11 spi_rom_do 12 spi_rom_di 13 vddio 14 insertion_detect bulk_cap 15 pd_detect safedb_en 16 chg_emu_en nc 17 vmon 18 imon 19 vddio 20 vdd18_cap 21 pd_vdd18 22 pd_en_n 23 pd_id 24 pd_data 25 vbus_discharge 26 test 27 reset_n 28 vsel0_n
UPD1001 ds00001759b-page 8 ? 2014 microchip technology inc. 2.1.3 32-sqfn system level diagrams figure 2-2 and figure 2-3 provide typical system level diagrams of t he UPD1001 for 32-a (stan dard-a receptacle) and 32-b (standard-b receptacle) applications, respectively. 29 vsel1_n 30 vsel2_n 31 vsel3_n 32 fault_n exposed pad vss figure 2-2: config uration 32-a system-level diagram table 2-1: 32-sqfn package pin assignments (continued) pin number configuration 32-a name configuration 32-b name microchip UPD1001 32-sqfn configuration 32-a spi_rom_clk spi_rom_di spi_rom_do spi_rom_ce_n to spi rom vss + + pd_en_n chg_emu_en cfg_sel0 vddio cfg_sel1 vddio usb power delivery enabled standard-a receptacle port power controller vddio vmon imon csa + cmp ifault d+ d- gnd pd_detect 1 vbus_discharge vbus couple/filter pd_data pd_id pd_detect insertion_detect insertion_detect 2 insertion_detect 1 shield 35.7k 5.1k vddio fault_n vsel0_n vsel1_n vsel2_n vsel3_n
? 2014 microchip technology inc. ds00001759b-page 9 UPD1001 figure 2-3: config uration 32-b system-level diagram microchip UPD1001 32-sqfn configuration 32-b vsel0_n vsel1_n spi_rom_clk spi_rom_di spi_rom_do spi_rom_ce_n to spi rom vss + + pd_en_n vsafedb_en cfg_sel0 vddio cfg_sel1 vddio usb power delivery enabled standard-b receptacle dead battery vddio vmon imon csa + cmp ifault gnd id vbus_discharge vbus couple/filter pd_data pd_id bulk_cap filter cap bank 35.7k 5.1k vddio fault_n vsel2_n vsel3_n
UPD1001 ds00001759b-page 10 ? 2014 microchip technology inc. 2.2 pin descriptions table 2-2: pin descriptions name symbol buffer type description power delivery power deliv- ery cable id pd_id aio usb connector signal used to indicate a high-current power delivery capable cable is inserted. this signal is to be connected to the pd_id pi n located on the usb pd standard-b receptacle. power deliv- ery vbus data pd_data aio modulated power delivery vbus data. requires in-line isolation filter. reference schematic available on request. power deliv- ery detect pd_detect is (pu) this signal is to be connected to the pd detect pins located on the usb pd standard-a receptacle. this sig- nal is pulled high via an internal pull-up resistor by default. assertion (low value) of pd_detect qualifies a usb-pd plug detection event. note: this function is only available in specific device configurations. power delivery enable pd_en_n o8 this active low signal controls output of the power supply voltage onto vbus. this signal will typically always be asserted, even when vbus is 5 v. miscellaneous vbus voltage monitor vmon ai stepped down voltage representation of the vbus volt- age. this signal must be connected to a voltage divider circuit as specified in section 2.4, "power connection diagram," on page 18 . voltage must not exceed 5 v on this signal. refer to section 3.4, "voltage/current moni- tors (vmon/imon)," on page 25 for additional informa- tion. charger cur- rent monitor imon ai voltage representation of the charger current. this signal should be fed by a current se nse amplifier tuned to output 3.0 v when 6.0 a is flowing on vbus. voltage must not exceed 5 v on this signal. refer to section 3.4, "voltage/ current monitors (vmon/imon)," on page 25 for addi- tional information. power supply fault indicator fault_n od8 this active low signal can be connected to an external led or soc and is used by the device to indicate power supply exceptions/failures as determined by the inte- grated voltage/current monitors. refer to section 3.4, "voltage/current monitors (vmon/imon)," on page 25 for additional information. power deliv- ery profile configuration selector 0 cfg_sel0 aio this pin is used in conjunction with cfg_sel1 to select the power delivery profile of the device via an externally connected rc circuit. refer to section 3.3, "configuration selection (cfg_sel0/cfg_sel1)" for additional infor- mation.
? 2014 microchip technology inc. ds00001759b-page 11 UPD1001 power deliv- ery profile configuration selector 1 cfg_sel1 aio this pin is used in conjunction with cfg_sel0 to select the power delivery profile of the device via an externally connected rc circuit. refer to section 3.3, "configuration selection (cfg_sel0/cfg_sel1)" for additional infor- mation. source voltage select 0 vsel0 od8 this pin is used in conjunction with vsel1 to select the correct source voltage from the dc-to-dc or ac-to-dc solution. vsel1 and vsel0 select the voltage value from the supported voltage capabilities in ascending order with vsel0 being the least significant bit (see examples below). for example, if an adapter supports 5, 9, and 20 v capa- bilities, the vsel1 and vsel0 selections will be as fol- lows: vsel1 vsel0 0 0: 5v 0 1: 9v 1 0: 20 v 1 1: reserved in another example, if an ad apter supports 5, 9, 12, and 20 v capabilities, the vsel1 and vsel0 selections will be as follows: vsel1 vsel0 0 0: 5v 0 1: 9v 1 0: 12 v 1 1: 20 v for a mapping of the vsel1 / vsel0 voltage assignments for each cfg_sel1 / cfg_sel0 configuration profile, refer to table 3-3: 32-sqfn cfg_selx configuration assignments on page 21 . note: this function is only available in specific device configurations. source voltage select 1 vsel1 od8 this signal is used in conjunction with vsel0 to select the correct source voltage from the dc-to-dc or ac-to- dc solution. vsel0 and vsel1 select the voltage value from the supported voltage capabilities in ascending order. refer to the vsel0 definition for additional information. note: this function is only available in specific device configurations. table 2-2: pin descri ptions (continued) name symbol buffer type description
UPD1001 ds00001759b-page 12 ? 2014 microchip technology inc. source voltage select 0 vsel0_n od8 this active low signal is one in a series of output pins ( vsel0_n , vsel1_n , vsel2_n , and vsel3_n ) used to select the correct source vo ltage from the dc-to-dc solu- tion. each vselx_n pin is dedicated to one voltage, assigned in order of increasing supported voltage. for example, if 5, 12 and 20 v capabilities are supported, the vselx_n selections will be as follows: vsel0_n = 5 v vsel1_n = 12 v vsel2_n = 20 v vsel3_n = reserved in another example, if onl y 5 and 20 v care supported, the vselx_n selections will be as follows: vsel0_n = 5 v vsel1_n = 20 v vsel2_n = reserved vsel3_n = reserved the vselx_n pins are also used to set the overvoltage protection (ovp) voltage on the vmon pin. the ovp fault will trigger when the measured voltage on vmon is 10% above the selected voltage setting. for a mapping of the vselx_n voltage assignments for each cfg_sel1 / cfg_sel0 configuration profile, refer to section 3.3, "configuration selection (cfg_sel0/ cfg_sel1)," on page 20 . note: this function is only available in specific device configurations. source voltage select 1 vsel1_n od8 this active low signal is one in a series of output pins ( vsel0_n , vsel1_n , vsel2_n , and vsel3_n ) used to select the correct source vo ltage from the dc-to-dc solu- tion. each vselx_n pin is dedicated to one voltage, assigned in order of increasing supported voltage. refer to the vsel0_n definition for additional informa- tion. note: this function is only available in specific device configurations. table 2-2: pin descri ptions (continued) name symbol buffer type description
? 2014 microchip technology inc. ds00001759b-page 13 UPD1001 source voltage select 2 vsel2_n od8 this active low signal is one in a series of output pins ( vsel0_n , vsel1_n , vsel2_n , and vsel3_n ) used to select the correct source vo ltage from the dc-to-dc solu- tion. each vselx_n pin is dedicated to one voltage, assigned in order of increasing supported voltage. refer to the vsel0_n definition for additional informa- tion. note: this function is only available in specific device configurations. source voltage select 3 vsel3_n od8 this active low signal is one in a series of output pins ( vsel0_n , vsel1_n , vsel2_n , and vsel3_n ) used to select the correct source vo ltage from the dc-to-dc solu- tion. each vselx_n pin is dedicated to one voltage, assigned in order of increasing supported voltage. refer to the vsel0_n definition for additional informa- tion. note: this function is only available in specific device configurations. vbus discharge vbus_discharge o8 this active high output is used to drive a power nfet to discharge vbus during high-to-low voltage transitions in order to achieve vsafe0v. when asserted, the external mosfet should conduct to gnd through a current limit- ing resistor. this signal de-asserts when the vmon sig- nal voltage reaches a preset value (a percentage of the destination voltage). emulation enable chg_emu_en o8 this active high output signal can be used to drive the emulation enable pin of a microchip ucs1001 or similar device that supports bc 1.2. the device will assert this signal whenever operating at vsafe5v without a pd con- tract. whenever a pd contract is established (even at 5 v), this signal is de-asserted. note: this function is only available in specific device configurations. table 2-2: pin descri ptions (continued) name symbol buffer type description
UPD1001 ds00001759b-page 14 ? 2014 microchip technology inc. insertion detect insertion_detect is (pu) this active low input signal should be connected to the insertion detect pin on the usb standard-a (std-a) receptacle. this signal is pulled high via an internal pull- up resistor by default. assertion (low value) qualifies a std-a plug insertion event and triggers transition out of the ?startup? state of the source policy engine. the device firmware implemen ts cold socket detection using the insertion_detect signal. even when operating as a provider, if the signal is high, the device will not output voltage on vbus. vsafe5v will only be output upon assertion of this signal (low). note: cold socket (insertion detect) is an optional feature in the usb pd specification. if this fea- ture is not being used in a design, the inser- tion_detect signal must be grounded. note: this function is only available in specific device configurations. dead battery enable vsafedb_en o8 this active high output signal is used to enable the dead battery supply on a usb standard-b (std-b) receptacle (consumer/provider) ac adapter. when no voltage has been detected on vbus, this signal is asserted every 10 s to back power an attached provider/consumer and determine whether the attached device has specified to be powered per the dead battery mechanisms specified in the pd specification. note: this function is only available in specific device configurations. bulk capacitance enable bulk_cap o8 this active high output signal is used to enable/disable the source bulk capacitance charging. in dual-role ports it is used to disable the bulk capacitance when operating as a consumer. note: this function is only available in specific device configurations. system fault detect ifault is this active high signal is used by the power supplying device to notify when a system fault condition has occurred. this input is typically used for an over-current or over-voltage condition, but can be used for any system related failure. an external comparator should be used to filter any external noise on this input. the device firmware automatically handles all power exceptions by shutting down the power supply, re-enabling it, and restarting pd negotiation until successful. note: the board design must ensure this signal is in a valid state by the time pd_en_n asserts. system reset reset_n is (pu) system reset. this signal is active low. te s t test is test signal. this signal is used for internal purposes only and must be connected to ground through a 1 k resistor for normal operation. table 2-2: pin descri ptions (continued) name symbol buffer type description
? 2014 microchip technology inc. ds00001759b-page 15 UPD1001 no connect nc - no connect. for proper operation, this signal must not be connected. spi rom interface spi rom clock spi_rom_clk o8 spi clock output to the serial rom spi rom chip enable spi_rom_ce_n o8 this is the active low spi rom chip enable output. if the spi rom interface is enabled, this signal should be pulled up to the spi rom vcc rail. spi rom data in spi_rom_di is spi rom data in spi rom data out spi_rom_do o8 (pd) spi rom data out note: this signal must be pulled-up to vddio with an external 10 k resistor for proper opera- tion. power/ground vtr supply input vtr p +3.3 to +5.0 v main power supply input. this signal must be connected to a 2.2 f capacitor to ground. refer to figure 2-4 for additional power connection information. +3.3 to +5.0 v variable volt- age i/o power vddio p +3.3 v to +5.0 v variable i/o power supply input. refer to figure 2-4 for additional power connection information. note: when using internal +3.3 v regulator, these pins must be externally connected to vdd33_cap . +5.0 v vbus input vbus p optional +5.0 v auxiliary power input for the integrated power switch. this signal must be connected to ground or to a +5.0 v voltage source with a 2.2 f capacitor to ground. refer to figure 2-4 for additional power connec- tion information. note: for externally powered devices (ac/dc adapters, charging adapters, etc.) this power pin is typically connected to ground. note: this function is only available in specific device configurations. +1.8v power delivery pd_vdd18 p +1.8 v power for power delivery phy. refer to figure 2-4 for additional power connection information. note: this pin must be connected to vdd18_cap pin externally when using the internal vdd18 regulator. +1.8 v power capacitance vdd18_cap p this pin is used to provide capacitance for the integrated +1.8 v regulator and must be connected to a 1 f (<100 m esr) capacitor to ground. refer to figure 2-4 for additional power connection information. table 2-2: pin descri ptions (continued) name symbol buffer type description
UPD1001 ds00001759b-page 16 ? 2014 microchip technology inc. +1.8 v analog power capacitance vdd18a_cap p this pin is used to provide capacitance for the integrated +1.8 v analog regulator and must be connected to a 1 f (<100 m esr) capacitor to ground. refer to figure 2-4 for additional power connection information. +3.3 v power capacitance vdd33_cap p +3.3 v regulator output. this pin must be connected to a 1f (<100m esr) capacitor to ground. refer to figure 2-4 for additional power connection information. integrated power switch capacitance vsw_cap p this pin is used to provide capacitance for the integrated power switch and must be connected to a 1 f (<100 m esr) capacitor to ground. refer to figure 2-4 for addi- tional power connection information. note: this function is only available in specific device configurations. ground vss p common ground. this exposed pad must be connected to the ground plane with a via array. table 2-2: pin descri ptions (continued) name symbol buffer type description
? 2014 microchip technology inc. ds00001759b-page 17 UPD1001 2.3 buffer types note: all signals are 5 v tolerant. table 2-3: buffer types buffer type description is schmitt-triggered input o8 output with 8 ma sink and 8 ma source od8 open-drain output with 8 ma sink pu 50 a (typical) internal pull-up. unless other wise noted in the signal description, internal pull-ups are always enabled. note: internal pull-up resistors prevent unconnect ed inputs from floating. do not rely on internal resistors to drive signals exte rnal to the device. when connected to a load that must be pulled high, an ex ternal resistor must be added. pd 50 a (typical) internal pull-down. unless other wise noted in the signal description, internal pull-downs are always enabled. note: internal pull-down resistors prevent unconn ected inputs from floating. do not rely on internal resistors to drive signals exte rnal to the device. when connected to a load that must be pulled low, an external resistor must be added. ai analog input aio analog bi-directional p power pin
UPD1001 ds00001759b-page 18 ? 2014 microchip technology inc. 2.4 power connection diagram figure 2-4 details the various power connection requirements. figure 2-4: power connection diagram microchip UPD1001 vdd33_cap vddio vss vddio 0.1uf 0.1uf 0.1uf 1.0uf pd_vdd18 vdd18_cap 0.1uf 1.0uf vdd18a_cap 0.1uf 1.0uf vtr 2.2uf 0.1uf vbus vsw_cap 1.0uf
? 2014 microchip technology inc. ds00001759b-page 19 UPD1001 3.0 functional descriptions this chapter provides functional descri ptions for the various device sub-systems: ? resets ? power management ? configuration selection (cfg_sel0/cfg_sel1) ? voltage/current monitors (vmon/imon) ? spi rom controller 3.1 resets the device includes the following reset controls: ? power-on reset (por) ? external chip reset ( reset_n ) a system reset event via the external reset_n pin or por causes the following: ? all registers are set to their default values ? pins are placed into their default state the rising and falling power-on reset thresholds for each power supply are detailed in ta b l e 3 - 1 . after power up, the por initially de-asserts after the rising threshold is passed. in the event that the supply drops below the falling threshold, the por will assert. the po r stays asserted until the rising threshold is once again crossed. 3.2 power management the device will enter low power modes based on the state of the connection to the power delivery port partner. the low power connection states are defined for the device operat ing as a provider (provider/c onsumer) or a consumer (con- sumer/provider). the device provides the following power states: ? provider: wait insert state ? consumer: sink discovery state 3.2.1 provider (or provider/consumer) power state the device provider configuration will enter a low power mode when it is not connected to a port partner and when a standard-a plug is not inserted in the receptacle. 3.2.1.1 wait insert state in the wait insert state, the device utilizes the insertion detect feature to enter a standby mode when waiting for a stan- dard-a plug to be inserted in the receptacle. on insertion of a standard-a plug, the dev ice will exit from the standby mode, initiate operation by enabling t he supply output to 5vsafe, and initia te the discovery of a port partner. 3.2.2 consumer (or consumer/provider) power state the device consumer configurati on enters a standby mode when it is not connected to a provider. 3.2.2.1 sink discovery state in the sink discovery state, the device waits for the presence of vbus to i ndicate a connection to provider. the device enters a standby state when waiting for the presence of vbus. at the presence of vbus, the consumer exits the standby state and resumes full operation to establis h a negotiated power contra ct with the provider. table 3-1: por thresholds por rising threshold falling threshold vddio supply 2.7 v 2.35 v vtr supply 2.85 v 2.7 v
UPD1001 ds00001759b-page 20 ? 2014 microchip technology inc. 3.3 configuration selection ( cfg_sel0 / cfg_sel1 ) the UPD1001 provides a resistor/capacitor identification detection in terface which is utilized to set various device con- figuration parameters via the configuration select pins: ? cfg_sel0 ? cfg_sel1 each configuration select pin can discr iminate a number of quantized rc constants. the judicious selection of rc val- ues provides a low cost means for system element configurat ion identification. the config uration select pins measure the charge/discharge time for the rc circuit connected to it (shown in figure 3-1 ), providing the ability to differentiate 16 unique ?bins? for each configuration select pin. the resi stor and capacitor values for each configuration select bin are defined in ta b l e 3 - 2 . note: cfg_sel0 and cfg_sel1 bin definitions are identical. figure 3-1: cfg_sel0/cfg_ sel1 resistor-capacitor circuit connections table 3-2: cfg_selx pin resist or-capacitor bin allocation bin r x (+/-1%) c x (+/-5%) 12.70k none 22.70k 470 pf 34.87k 470 pf 48.66k 470 pf 5 15.40 k 470 pf 62.70k 4.7 nf 74.87k 4.7 nf 88.66k 4.7 nf 9 15.40 k 4.7 nf 10 2.70 k 47.0 nf 11 4.87 k 47.0 nf 12 8.66 k 47.0 nf 13 15.40 k 47.0 nf 14 2.70 k 470 nf 15 4.87 k 470 nf 16 8.66 k 470 nf v d d i o r 1 c 1 cfg_sel0 microchip UPD1001 v d d i o r 2 c 2 cfg_sel1
? 2014 microchip technology inc. ds00001759b-page 21 UPD1001 by selecting specific bins on both the cfg_sel0 and cfg_sel1 pins, predefined configurations may be selected. these assignments configure multiple parame ters of the device, including the following: ? pin configuration ? receptacle type ? usb power delivery role selection a list of the configuration assign ments along with the corresponding cfg_sel0 and cfg_sel1 bin settings, are detailed in the following section: ? section 3.3.1, "32-sqfn cfg_selx co nfiguration assignments," on page 21 for details on each configurable parameter, refer to the following sub-sections. captive a cable to micro-b solutions are not listed in the cfg_selx assignment tables, but can be addressed as fol- lows: - when pd_detect and insertion_detect pin are grounded, the device infers a pd cable is always attached and the source capabilities are limited to 3a. -the cfg_selx pin combinations for regular standard-a soluti ons can be used for equivalent capabilities. captive b cable to a solutions are not listed in the cfg_selx assignment tables, but can be addressed as follows: - the proper capacitor marker, as per the usb power delivery specification , should be positioned on the pd_id pin to signal a 3a or 5a cable. -the cfg_selx pin combinations for regular standard-b soluti ons can be used for equivalent capabilities. note: only the bin combinations defined in the following tables are valid. all other bin combinations are reserved and must not be used. 3.3.1 32-sqfn cfg_selx configuration assignments table 3-3 details the various 32-sqfn cfg_selx configuration assignments. table 3-3: 32-sqfn cfg_selx configuration assignments config. # 32-sqfn pin config. receptacle type pd consumer abilities pd provider abilities vsel0_n vsel1_n vsel2_n vsel3_n cfg_sel1 bin cfg_sel0 bin 1 32-a std-a none profile 1 5 - - - 1 1 2 32-a std-a none profile 1, 5v@3a 5 - - - 1 2 3 32-a std-a none profile 1, 5v@5a 5 - - - 1 3 4 32-a std-a none profile 1, 9v@2a 5 9 - - 1 4 5 32-a std-a none profile 1, 20v@3a 5 20 - - 1 5 6 32-a std-a none profile 1, 20v@5a 5 20 - - 1 6 7 32-a std-a none profile 2 5 12 - - 1 7 8 32-a std-a none profile 2, 9v@2a 5 9 12 - 1 8 9 32-a std-a none profile 3 5 12 - - 1 9 10 32-a std-a none profile 3, 5v@3a 5 12 - - 1 10 11 32-a std-a none profile 3, 9v@3a 5 9 12 - 1 11 12 32-a std-a none profile 3, 5v@3a, 9v@3a 5 9 12 - 1 12 13 32-a std-a none profile 3, 5v@3a, 9v@3a, 16v@3a 5 9 12 16 1 13 14 32-a std-a none profile 3, 9v@3a, pp-200 5 9 12 - 1 14 15 32-a std-a none profile 3, pp-200 5 12 - - 1 15 16 32-a std-a none profile 4 5 12 20 - 1 16 17 32-a std-a none profile 4, 5v@3a 5 12 20 - 2 1 18 32-a std-a none profile 4, 9v@3a 5 9 12 20 2 2
UPD1001 ds00001759b-page 22 ? 2014 microchip technology inc. 19 32-a std-a none profile 4, 5v@3a, 9v@3a 5 9 12 20 2 3 20 32-a std-a none profile 4, 5v@3a, 16v@3a 5 12 16 20 2 4 21 32-a std-a none profile 4, 9v@3a, pp-200 5 9 12 20 2 5 22 32-a std-a none profile 4, 9v@5a, pp-200 5 9 12 20 2 6 23 32-a std-a none profile 4, pp-200 5 12 20 - 2 7 24 32-a std-a none profile 5 5 12 20 - 2 8 25 32-a std-a none profile 5, 5v@5a 5 12 20 - 2 9 26 32-a std-a none profile 5, 5v@5a, 16v@5a 5 12 16 20 2 10 27 32-a std-a none profile 5, 5v@5a, 9v@5a 5 9 12 20 2 11 28 32-a std-a none profile 5, pp-200 5 12 20 - 2 12 29 32-a std-a none profile vsafe5v-l, 20v@3a 5 20 - - 2 13 30 32-a std-a none profile vsafe5v-l, 20v@5a 5 20 - - 2 14 31 32-b std-b na (profile vsafe5v-nc) profile 1 5 - - - 2 15 32 32-b std-b na (profile vsafe5v-nc) profile 1, 5v@3a 5 - - - 2 16 33 32-b std-b na (profile vsafe5v-nc) profile 1, 5v@5a 5 - - - 3 1 34 32-b std-b na (profile vsafe5v-nc) profile 1, 9v@2a 5 9 - - 3 2 35 32-b std-b na (profile vsafe5v-nc) profile 1, 20v@3a 5 20 - - 3 3 36 32-b std-b na (profile vsafe5v-nc) profile 1, 20v@5a 5 20 - - 3 4 37 32-b std-b na (profile vsafe5v-nc) profile 2 5 12 - - 3 5 38 32-b std-b na (profile vsafe5v-nc) profile 2, 9v@2a 5 9 12 - 3 6 39 32-b std-b na (profile vsafe5v-nc) profile 3 5 12 - - 3 7 40 32-b std-b na (profile vsafe5v-nc) profile 3, 5v@3a 5 12 - - 3 8 41 32-b std-b na (profile vsafe5v-nc) profile 3, 5v@3a, 9v@3a 5 9 12 - 3 9 42 32-b std-b na (profile vsafe5v- nc) profile 3, 5v@3a, 9v@3a, 16v@3a 5 9 12 16 3 10 43 32-b std-b na (profile vsafe5v-nc) profile 4 5 12 20 - 3 11 44 32-b std-b na (profile vsafe5v-nc) profile 4, 5v@3a 5 12 20 - 3 12 45 32-b std-b na (profile vsafe5v-nc) pr ofile 4, 5v@3a, 16v@3a 5 12 16 20 3 13 46 32-b std-b na (profile vsafe5v-nc) profile 4, 5v@3a, 9v@3a 5 9 12 20 3 14 47 32-b std-b na (profile vsafe5v-nc) profile 4, pp-200 5 12 20 - 3 15 48 32-b std-b na (profile vsafe5v-nc) profile 5 5 12 20 - 3 16 49 32-b std-b na (profile vsafe5v-nc) profile 5, 5v@5a 5 12 20 - 4 1 50 32-b std-b na (profile vsafe5v-nc) pr ofile 5, 5v@5a, 16v@5a 5 12 16 20 4 2 51 32-b std-b na (profile vsafe5v-nc) profile 5, 5v@5a, 9v@5a 5 9 12 20 4 3 52 32-b std-b na (profile vsafe5v-nc) profile 5, pp-200 5 12 20 - 4 4 53 32-b std-b na (profile vsafe5v-nc) profile vsafe5v-l, 20v@3a 5 20 - - 4 5 54 32-b std-b na (profile vsafe5v-nc) profile vsafe5v-l, 20v@5a 5 20 - - 4 6 table 3-3: 32-sqfn cfg_selx configuration assignments (continued) config. # 32-sqfn pin config. receptacle type pd consumer abilities pd provider abilities vsel0_n vsel1_n vsel2_n vsel3_n cfg_sel1 bin cfg_sel0 bin
? 2014 microchip technology inc. ds00001759b-page 23 UPD1001 3.3.2 pin configuration the UPD1001 32-sqfn package provides se lectable pin configurations via the cfg_sel0 and cfg_sel1 pins, as defined in table 3-3, "32-sqfn cfg_selx configuration assignments" . table 1-1, "UPD1001 package/pin configura- tion summary" provides a summary of the available pin configurations. refer to section 2.1, "32-pin sqfn (32-sqfn)" for details on the corresponding package pin definitions. 3.3.3 receptacle type the usb receptacle type is configurable bet ween standard-a and standard-b types via the cfg_sel0 and cfg_sel1 pins, as defined in table 3-3 . each of these receptacle type settings is detailed below. 3.3.3.1 standard-a (std-a) the standard-a setting informs the device that the designer is utilizing a standard-a usb pd receptacle. 3.3.3.2 standard-b (std-b) the standard-b setting informs the device that the designer is utilizing a standard-b usb pd receptacle. 3.3.4 usb power delivery role selection depending on the receptacle type selected, the device may support and swap consumer and provider roles. standard-a receptacle (captive cable or otherwise) ac ad apters only support the provid er role, and therefore do not support role swap. standard-b receptacle ac adapters are consumer/providers that start operation in their default role of consumer and support role swapping. swapping rules for standard-b ac adapters are defined as follows: ? when operating as a consumer: - upon starting up, the ac adapter autom atically initiates a swap request to its partner to become a provider. if the partner rejects the request, the ac adapter will remain in its consumer role until the partner requests a swap. - if the ac adapter receives a swap request from its part ner to become a consumer, it automatically accepts it. ? when operating as a provider - the ac adapter will never initiate a swap request to its partner to become a consumer. - if the ac adapter receives a swap request from its part ner to become a consumer, it automatically accepts it and will remain in the consumer role (until the partner requests another swap back to provider, or there is a hard reset or other exception condition that causes the protocol to be re-initiated from startup). the reason for this behavior is that the partner may have its own other external power which it decided to use instead of the ac adapter. note 1: all ac adapters will only operate when connected to exte rnal ac power. an ac adapter that is not plugged to the wall power supply will not be powered from its partner and will therefore not operate at all. 2: standard-b receptacle ac adapters also support dead battery detection and can perform dead battery implicit swaps as per the pd specification. the various power delivery provider and consumer capa bilities are detailed in the following sub-sections. 3.3.4.1 power delivery provider capabilities the usb pd provider capabilities may be selected via the cfg_sel0 and cfg_sel1 pins, as defined in section 3.3, "configuration selection (cfg_sel0/cfg_sel1)" . each of the pd provider capabilities are detailed below. when capabilities are combined, it is possible that a device can support two or more curr ents for the same volt age. in this case, the device will only advertise one voltage with the highest current. for example, a device that specifies support for ?profile 2 + 5v@3a? must support 5v@2a, 12v@1.5a and 5v@ 3a. in this case, the device will advertise only two power da ta objects (pdo): 5v@3a and 12v@1.5a. the device will not explicitly advertise 5v@2a. however, a consumer that requires 5v@2a will request the 5v@ 3a pdo but only consume 2a.
UPD1001 ds00001759b-page 24 ? 2014 microchip technology inc. vsafe5v-l (5v@1a) the provider capability profile for vsafe5v legacy (5v@1a) in dicates that the UPD1001 supports providing 5 v at 1 a. this is typically used in dual-role ports that offer no real capability at 5 v (e.g., a standard-b consumer-provider ac adapter port that only supports 20 v), but need to abide by the usb power delivery specification requirement that at least one vsafe5v pdo be offered. therefore, the capabili ties of a legacy usb port (max 900 ma for usb 3.0) are included. profile 1 the provider capability profile 1 indicates that the up d1001 supports providing the voltages and currents needed to satisfy the usb pd profile 1, as defined by the usb power delivery specification (5v@2a). profile 2 the provider capability profile 2 indicates that the up d1001 supports providing the voltages and currents needed to satisfy the usb pd profile 2, as defined by the usb power delivery specification (5v@2a and 12v@1.5a). profile 3 the provider capability profile 3 indicates that the up d1001 supports providing the voltages and currents needed to satisfy the usb pd profile 3, as defined by the usb power delivery specification (5v@2a and 12v@3a). profile 4 the provider capability profile 4 indicates that the up d1001 supports providing the voltages and currents needed to satisfy the usb pd profile 4, as defined by the usb power delivery specification (5v@2a, 12v@3a, and 20v@3a). profile 5 the provider capability profile 5 indicates that the up d1001 supports providing the voltages and currents needed to satisfy the usb pd profile 5, as defined by the usb power delivery specification (5v@2a, 12v@5a, and 20v@5a). 5v@3a the provider capability 5v@3a indicates that the UPD1001 supports providing 5 v at 3 a. this option can be combined with other provider capability options. 5v@5a the provider capability 5v@5a indicates that the UPD1001 supports providing 5 v at 5 a. this option can be combined with other provider capability options. 9v@2a the provider capability 9v@2a indicates that the UPD1001 supports providing 9 v at 2 a. this option can be combined with other provider capability options. 9v@3a the provider capability 9v@3a indicates that the UPD1001 supports providing 9 v at 3 a. this option can be combined with other provider capability options. 9v@5a the provider capability 9v@5a indicates that the UPD1001 supports providing 9 v at 5 a. this option can be combined with other provider capability options. 16v@3a the provider capability 16v@3a indicate s that the UPD1001 supports providi ng 16 v at 3 a. this option can be com- bined with other provid er capability options. 16v@5a the provider capability 16v@5a indicate s that the UPD1001 supports providi ng 16 v at 5 a. this option can be com- bined with other provid er capability options. 20v@3a the provider capability 20v@3a indicate s that the UPD1001 supports providi ng 20 v at 3 a. this option can be com- bined with other provid er capability options. 20v@5a the provider capability 20v@5a indicate s that the UPD1001 supports providi ng 20 v at 5 a. this option can be com- bined with other provid er capability options.
? 2014 microchip technology inc. ds00001759b-page 25 UPD1001 peak power-capable setting 0b11 - 200% (pp-200) the peak power-capable 200% indicates that the UPD1001 su pports providing 200% of the current limit for a 1 ms time duration at 5% duty cycle. this will add the correct 0b11 bits to the pdo. 3.3.4.2 pd consumer capabilities ac adapters are not intended to be consumers. however, a need exists for standard-b receptacle (consumer/provider) ac adapters for powering notebooks through their pd enabl ed standard-a host ports. the power delivery specification requires any consumer port to at least support vsafe5v, so a minimal non-consuming capability is defined (vsafe5v- nc). the usb pd consumer capabilities may be selected via the cfg_sel0 and cfg_sel1 pins, as defined in section 3.3, "configuration selection (cfg_sel0/cfg_sel1)" . each of the pd consumer capabilities are detailed below. vsafe5v-nc (5v@0a) the consumer capability profile for vsafe5v non-consuming indicates to the UPD1001 that this solution must have only 5 v input sources and must not consume. this is typically used in dual-role ports that offer no capability in their default role (e.g., a standard-b c onsumer-provider ac adapter port). 3.4 voltage/current monitors ( vmon / imon ) 3.4.1 vmon the integrated voltage monitor utilizes the vmon pin to read a stepped down voltage representation of the vbus volt- age. this pin must be connected to a vo ltage divider circuit as specified in section 2.4, "power connection diagram," on page 18 . the device monitors the vbus voltage as a provider to manage the behavior of the power supply, detecting power supply transitions and over/under-voltage conditions. 3.4.1.1 power supply transitions using vmon , the device monitors the voltage on vbus to manage the transitions of the supply output. the supply power-on and power-off transitions are determined to be at t heir final states when reaching predefined voltage thresh- olds, as detailed in table 3-4 . the power-on threshold indicates when the supply has reached the defined voltage. the power-off threshold indicates when the supply output is di scharged. all voltage transitions are bound by an internal timer. if the voltage transition times out, the fault_n pin will be asserted until the power transition is successfully com- pleted. 3.4.1.2 overvoltage condition using vmon , the device monitors the voltage on vbus to detect an overvoltage condition on the supply output. the overvoltage condition is determined w hen the predefined overvoltage thre shold is crossed, as detailed in table 3-5 . on the occurrence of t he overvoltage condition: ? the supply output will turned off and discharged. ?the fault_n pin will be strobed approximately every 500ms. ? if more than 3 consecutive exceptions occur within a 4 second period, fault_n will be strobed approximately every 5 seconds. table 3-4: vmon power-on/o ff transition thresholds voltage threshold (v) min. typical max power-on -3- power-off -2-
UPD1001 ds00001759b-page 26 ? 2014 microchip technology inc. 3.4.1.3 undervoltage condition using vmon , the device monitors the voltage on vbus to detect an undervoltage condition on the supply output. the undervoltage condition is determined when the predefined undervoltage threshold is crossed, as detailed in ta b l e 3 - 6 . on the occurrence of the undervoltage condition: ? the supply output will turned off and discharged. ?the fault_n pin will be strobed approximately every 500ms. ? if more than 3 consecutive exceptions occur within a 4 second period, fault_n will be strobed approximately every 5 seconds. 3.4.2 imon the integrated current monitor utilizes the imon pin to read a voltage representation of the power supply output current. this pin should be fed by a current sense amplifier tuned to output 3.0 v when 6.0 a is flowing on vbus. on connection of a port partner and the completion of a negotiated power contract, the overcurrent thresh old is set based on the nego- tiated current. when the device is not connected to a port pa rtner, the overcurrent threshold will be set to the default level. on the occurrence of an overcurrent condition: ? the supply output will turned off and discharged. ?the fault_n pin will be strobed approximately every 500ms. ? if more than 3 consecutive exceptions occur within a 4 second period, fault_n will be strobed approximately every 5 seconds. table 3-5: vmon overvoltage thresholds voltage threshold (v) min. typical max 5v -6.06.9 9v - 10.4 12.0 12 v - 13.7 15.8 16 v - 18.1 20.9 20 v - 22.5 26.9 table 3-6: vmon undervoltage thresholds voltage threshold (v) min. typical max 5v -4.5- 9v -8.1- 12 v - 10.8 - 16 v - 14.4 - 20 v - 18.0 - table 3-7: imon overcurrent thresholds negotiated profile current overcurrent threshold (a) min. typical max 1.5 a -1.731.95 2a -2.302.60 3a -3.453.90 5a -5.756.50
? 2014 microchip technology inc. ds00001759b-page 27 UPD1001 note: only sourced currents (when the pd port is op erating as a provider) can be monitored by imon . if it is desired to monitor a sinking current (when the port is operating as a consumer), an external circuit should be used and the condition indi cated to the device via the ifault pin. 3.5 spi rom controller the device is capable of code executio n from an external spi rom. on power up, the firmware looks for an external spi flash device that contains a valid signature of 2dfu (device firmware upgrade) beginning at address 0xfffa. if a valid signature is found, then the ex ternal rom is enabled and the code exec ution begins at address 0x0000 in the external spi device. if a valid signature is not found, then execution continues from inter nal rom. the following sections describe the interface options to the external spi rom. note: microchip suggests using the sst 25 series serial flash family, such as the sst25vf064c. 3.5.1 operation of the hi-speed read sequence the spi controller will automatically handl e code reads going out to the spi rom ad dress. when the controller detects a read, the contro ller drops the spi_rom_ce_n , and puts out a 0x0b, followed by the 24-bit address. the spi controller then puts out a dummy byte. the next eight clocks clock in the first byte. when the first byte is clocked in a ready signal is sent back to the processor, and the processor gets one byte. after the processor gets the first byte, its address will change. if the address is one more t han the last address, the spi controller will clock out one more byte. if the address in anything other than one more th an the last address, the spi controller will terminate the transaction by taking spi_rom_ce_n high. as long as the addresses are sequential, the spi controller will keep clocking in data. figure 3-2: spi rom hi -speed read operation spi controller spi rom serial to parllel ce# clk si so UPD1001 address control cache spi_rom_di
UPD1001 ds00001759b-page 28 ? 2014 microchip technology inc. 3.5.2 operation of the dual hi-speed read sequence the spi controller also supports dual data mode (at 30 mh z spi speed only). when conf igured in dual mode, the spi controller will automatically handle reads going out to the spi rom. when the controller detects a read, the controller drops the spi_rom_ce_n , and puts out a 0x3b, followed by the 24-bit address. the spi controller then puts out a dummy byte. the next four clocks clock in the first byte. t he data appears two bits at a time on data out and data in. when the first byte is clocked in a ready signal is s ent back to the processor, and the processor gets one byte. after the processor gets the first byte, the address will change. if the address is one more than the last address, the spi controller will clock out one more byte. if the address in anything other than one more th an the last address, the spi controller will terminate the transaction by taking spi_rom_ce_n high. as long as the addresses are sequential, the spi controller will keep clocking in data. figure 3-3: spi rom hi -speed read sequence figure 3-4: spi rom dual hi-speed read operation spi_rom_ce_n spi_rom_clk spi_rom_do spi_rom_di 8 0b msb high impedance 15 16 123 4 05 7 6 d out add. 23 24 add. add. x 39 40 31 32 47 48 55 56 63 64 71 72 80 d out n n+1 d out n+2 d out n+3 d out n+4 msb msb spi controller spi rom 2-serial to 8-parallel ce# clk si so address control cache spi_rom_di UPD1001
? 2014 microchip technology inc. ds00001759b-page 29 UPD1001 3.5.3 32-byte cache there is a 32-byte pipeline cache, and associated with the cache is a base address pointer and a length pointer. once the spi controller detects a jump, the base address pointer is initialized to that address. as each new sequential data byte is fetched, the data is written into the cache, and the length is in cremented. if the sequent ial run exceeds 32 bytes, the base address pointer is incremented to indicate the last 32 bytes fetched. if the device does a jump, and the jump is in the cache address range, the fetch is done in 1 clo ck from the internal cache instead of an external access. 3.5.4 interface operation to spi port when not performing fast reads there is an 8-byte command buffer: spi_cmd_buf[7:0]; an 8-byte response buffer: spi _resp_buf[7:0]; and a length register that counts out the number of bytes: spi_cmd_len. additionally, there is a self-clearing go bit in the spi_ctl register. once the go bit is set, the device drops spi_rom_ce_n , and starts clocking. it will put out spi_cmd_len x 8 number of clocks. after the first byte , the command, has been sent out, and the spi_rom_di is stored in the spi_resp buffer. if the spi_cmd_len is longer than the spi_cmd_buf, don?t cares are sent out on the spi_rom_do line. this mode is used for program execution out of internal ram or rom. figure 3-5: spi rom dual hi-speed read sequence figure 3-6: spi rom internally-controlled operation spi_rom_ce_n spi_rom_clk spi_rom_do spi_rom_di 8 0b msb high impedance 15 16 123 4 05 7 6 d1 add. 23 24 add. add. x 39 40 31 32 44 47 48 51 52 55 56 59 d2 n n+1 d3 n+2 d4 n+3 d5 n+4 msb msb d1 d2 nn+1 d3 n+2 d4 n+3 d5 n+4 msb 43 bits-7,5,3,1 bits-7,5,3,1 bits-7,5,3,1 bits-7,5,3,1 bits-6,4,2,0 bits-6,4,2,0 bits-6,4,2,0 bits-6,4,2,0 bits-7,5,3,1 bits-6,4,2,0 spi controller spi rom spi_rsp_buf[7:0] spi_cmd_buf[3:0] spi_cmd_len ce# clk si so UPD1001
UPD1001 ds00001759b-page 30 ? 2014 microchip technology inc. 3.5.4.1 erase example to perform a sctr_erase, 32blk_erase, or 64blk_erase, the device writes 0x20, 0x 52, or 0xd8, respectively to the first byte of the command buffer, followed by a 3-byte address. the length of the transf er is set to 4 bytes. to do this, the device first drops spi_rom_ce_n , then counts out 8 clocks. it then puts out the 8 bits of command, followed by 24 bits of address of the location to be erased on the spi_rom_do pin. when the transfer is complete, the spi_rom_ce_n goes high, while the spi_rom_di line is ignored in this example. 3.5.4.2 byte program example to perform a byte program, the device writes 0x02 to the firs t byte of the command buffer, followed by a 3-byte address of the location that will be written to, and one data byte. the l ength of the transfer is set to 5 bytes. the device first drop s spi_rom_ce_n , 8 bits of command are clocked out, followed by 24 bits of address, and one byte of data on the spi_rom_do pin. the spi_rom_di line is not used in this example. figure 3-7: spi rom erase sequence figure 3-8: spi rom byte program spi_rom_ce_n spi_rom_clk 16 23 24 31 15 123 4 05 7 6 add. spi_rom_do spi_rom_di 8 command msb msb add. add. high impedance spi_rom_ce_n spi_rom_clk 16 23 24 31 15 39 123 4 05 7 6 0x00 spi_rom_do spi_rom_di 8 0xdb msb msb 0xfe /0xff data msb lsb 32 high impedance 0xbf
? 2014 microchip technology inc. ds00001759b-page 31 UPD1001 3.5.4.3 command only program example to perform a single byte command such as the following: ?wrdi ?wren ?ewsr ? chip_erase ? ebsy ? dbsy the device writes the opcode into the first byte of the spi_cmd_buf and the spi_cmd_len is set to one. the device first drops spi_rom_ce_n , then 8 bits of the command are clocked out on the spi_rom_do pin. the spi_rom_di is not used in this example. figure 3-9: spi rom co mmand only sequence spi_rom_ce_n spi_rom_clk 1234 057 6 spi_rom_do spi_rom_di command msb high impedance
UPD1001 ds00001759b-page 32 ? 2014 microchip technology inc. 3.5.4.4 jedec-id read example to perform a jedec-id command, the device writes 0x9f into the first byte of the spi_cmd_buf and the length of the transfer is 4 bytes. the device first drops spi_rom_ce_n , then 8 bits of the command are clocked out, followed by the 24 bits of dummy bytes (due to the length being set to 4) on the spi_rom_do pin. when the transfer is complete, the spi_rom_ce_n goes high. after the first byte, the data on spi_rom_di is clocked into the spi_rsp_buf. at the end of the command, there are three valid bytes in the spi_rsp_buf. in this example, 0xbf, 0x25, 0x8e. figure 3-10: spi rom jedec-id sequence spi_rom_ce_n spi_rom_clk spi_rom_do spi_rom_di 8 9f msb high impedance 11 12 13 14 15 16 123 4 05 7 6 10 9 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 bf 25 8e msb msb
? 2014 microchip technology inc. ds00001759b-page 33 UPD1001 4.0 operational characteristics 4.1 absolute maximum ratings* supply voltage ( vddio , vtr ) ( note 1 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 v to +6.0 v positive voltage on input signal pins, with respect to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+6.0 v negative voltage on input signal pins, with respect to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 v storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55 o c to +150 o c lead temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . refer to jedec spec. j-std-020 hbm esd performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +/-2 kv note 1: when powering this device from laboratory or system powe r supplies, it is important that the absolute max- imum ratings not be exceeded or device failure can result. some power supplies exhibit voltage spikes on their outputs when ac power is switched on or off. in addition, voltage transients on the ac power line may appear on the dc output. if this possibility exis ts, it is suggested to use a clamp circuit. *stresses exceeding those listed in th is section could cause permanent damage to the device. this is a stress rating only. exposure to absolute maximum rating conditions for extended periods may affect device reliability. functional operation of the device at any condit ion exceeding those indicated in section 4.2, "operating conditions**" , section 4.4, "dc specifications" , or any other applicable section of this specification is not implied. 4.2 operating conditions** supply voltage ( vtr ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . + 3.1 v to +5.3 v supply voltage ( vddio ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.1 v t o +3.47 v positive voltage on input signal pins, with respect to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+3.3 v negative voltage on input signal pins, with respect to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 v positive voltage on vmon and imon pins, with respect to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vddio negative voltage on vmon and imon pins, with respect to ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 v power supply rise time max t rt ( figure 4-1 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tbd ambient operating temperature in still air (t a ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . note 2 note2: 0 o c to +70 o c for commercial version, -40 o c to +85 o c for industrial version. **proper operation of the device is guaranteed onl y within the ranges specified in this section. figure 4-1: supply rise time model t 10% 10% 90% voltage t rt t 90% time 100% 3.3v vss vddio
UPD1001 ds00001759b-page 34 ? 2014 microchip technology inc. 4.3 power consumption this section details the power consumption of the device as measured during various modes of operation. power dis- sipation is determined by temperature, supply voltage, and external source/sink requirements. note: maximum values represent very short bursts of activi ty over a small amount of time. typical values repre- sent averaged current co nsumption over time. 4.4 dc specifications note3: this specification applies to all inputs and tri-stat ed bi-directional pins. internal pull-down and pull-up resistors add +/- 50 a per-pin (typical). table 4-1: device power consumption power state vtr supply current typical max units reset 0.325 3.5 ma provider mode wait insert state 1.2 16.2 ma legacy device connected 14.6 58.5 ma pd device connected 28.0 69.0 ma consumer mode sink discovery state / legacy device connected 10.0 45.0 ma pd device connected 28.0 69.0 ma table 4-2: dc electrical characteristics parameter symbol min typ max units is type input buffer low input level high input level negative-going threshold positive-going threshold schmitt trigger hysteresis (v iht - v ilt ) input leakage (v in = vss or vddio ) input capacitance v ili v ihi v ilt v iht v hys i ih c in -0.3 2.5 1.25 1.40 188 -9.79 1.35 1.65 225 0.8 vddio +0.3 1.55 1.76 250 7.14 3 v v v v mv na pf schmitt trigger schmitt trigger note 3 o8 type buffers low output level high output level v ol v oh vddio - 0.7 0.35 v v i ol = -8 ma i oh = 8 ma od8 type buffer low output level v ol 0.35 v i ol = -8 ma
? 2014 microchip technology inc. ds00001759b-page 35 UPD1001 4.5 ac specifications this section details the various ac timing specifications of the device. 4.5.1 reset timing figure 4-2 illustrates the reset_n timing requirements. assertion of reset_n is not a requirement. however, if used, it must be asserted for the minimum period specified. refer to section 3.1, "resets," on page 19 for additional information on resets. figure 4-2: reset_n timing table 4-3: reset_n timing symbol description min typ max units t rstia reset_n input assertion time 1 s reset_n t rstia
UPD1001 ds00001759b-page 36 ? 2014 microchip technology inc. 4.5.2 spi rom controller timing the following specifies the spi rom controller timing requirements for the device. 4.5.3 usb power delivery signal timing all usb power delivery signals ( pd_data , pd_id ) conform to the voltage, power, and timing characteristics/specifica- tions as set forth in the usb power deli very specification. please refer to the usb power delivery specification , avail- able at http://www.usb.org. figure 4-3: spi rom controller timing table 4-4: spi rom controller timing values symbol description min typ max units t fc clock frequency 46.86 48 48.62 mhz t ceh chip enable ( spi_rom_ce_en ) high time 50 ns t clq clock to input data 15 ns t dh input data hold time 0.70 3 4.52 ns t os output setup time 5.35 7 8.28 ns t oh output hold time 11.57 13 15.22 ns t ov clock to output valid 1.16 2 3.3 ns t cel chip enable ( spi_rom_ce_en ) low to first clock 12 ns t ceh last clock to chip enable ( spi_rom_ce_en ) high 12 ns spi_rom_clk spi_rom_di spi_rom_do spi_rom_ce_n t cel t fc t clq t ceh t dh t oh t os t ov t oh
? 2014 microchip technology inc. ds00001759b-page 37 UPD1001 5.0 package outline 5.1 32-sqfn note: for the most current package drawings, se e the microchip packaging specification at: http://www.microchip.com/packaging. figure 5-1: 32-sqfn package note: for the most current package drawings, see the microchip packaging specification at http://www.microchip.com/packaging
UPD1001 ds00001759b-page 38 ? 2014 microchip technology inc. 6.0 revision history table 6-1: revision history revision level & date section/figure/entry correction ds00001759b (12-02-14) table 3-4 , ta b l e 3 - 5 , table 3-6 , and table 3-7 added imon/vmon thresholds (was tbd). section 4.5, "ac specifications," on page 35 removed ?vmon/imon fault recovery tim- ing? and ?ifault recovery timing? sections. table 3-2, ?cfg_selx pin resistor- capacitor bin allocation,? on page 20 updated cx tolerance to +/-5%. table 4-1, ?device power consump- tion,? on page 34 updated power consumption table. all: cover, intro removed ?programmable? from part description. all: cover, intro, pin descriptions, pack- age drawings, ordering codes removed 28-tssop package option. ds00001759a initial release
? 2014 microchip technology inc. ds00001759b-page 39 UPD1001 the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site con- tains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), te chnical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of semi- nars and events, listings of microchip sales offi ces, distributors and factory representatives customer change notification service microchip?s customer notification servic e helps keep customers current on microc hip products. subscribers will receive e-mail notification whenever there are changes, updates, revisi ons or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under ?support?, click on ?customer change notifi- cation? and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this docu- ment. technical support is available through the web site at: http://microchip.com/support
UPD1001 ds00001759b-page 40 ? 2014 microchip technology inc. product identification system to order or obtain information, e.g., on pricing or de livery, refer to the factor y or the listed sales office . device: UPD1001 tape and reel option: blank = standard packaging (tray) t = tape and reel ( note 1 ) temperature range: a= 0 c to +70 c (commercial) ai = -40 c to +85 c (industrial) package: mq = 32-pin sqfn examples: a) UPD1001-a/mq tray, commercial temp., 32-pin sqfn b) UPD1001t-ai/mq tape & reel, industrial temp., 32-pin sqfn note 1: tape and reel identifier only appears in the catalog part number description. this identifier is used for ordering purposes and is not printed on the device package. check with your microchip sales office for package availability with the tape and reel option. part no. device tape and reel option / temperature range xx [x] xx - package
? 2014 microchip technology inc. ds00001759b-page 41 UPD1001 information contai ned in this publicati on regarding device app lications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with yo ur specifications. microchip make s no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fi tness for purpose . microchip disclaims all liability arising from this information and its use. use of micro- chip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemn ify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, impl icitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, flashf lex, flexpwr, jukeblox, k ee l oq , k ee l oq logo, kleer, lancheck, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic 32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technolog y incorporated in the u.s.a. and other countries. the embedded control solutions company and mtouch are registered tr ademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, ecan, in-circuit serial programming, icsp, inter-chip connectivity, kleernet, kleernet logo, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem .net, pickit, pictail, righttouch logo, real ice, sqi, serial quad i/o, total endurance, tsharc, usbcheck, varisense, view span, wiperlock, wireless dna, and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchi p technology incorporated in the u.s.a. silicon storage technology is a regi stered trademark of microchip tech nology inc. in other countries. gestic is a registered trademarks of microc hip technology germany ii gmbh & co. kg, a s ubsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2014, microchip technology incorporated, printed in the u.s.a., all rights reserved. isbn: 9781632768452 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip pr oducts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digita l millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperi pherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 ==
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